Problem $1(20$ points$)$

Suppose that a processor with a load$/$store architecture has a clock rate of $2\mathrm{.}8$GHz$,$ with the

ideal CPI of $1\mathrm{.}2.$ The typical applications run on this processor contain a mix of $60\%$ arithmetic

and logic instructions, $20\%$ load and store instructions and $20\%$ conditional branches

instructions. The processor accesses the memory through separate data and instruction cache.

An average of $1\%$ of the instructions produce an instruction miss, while $5\%$ of the data accesses

are cache misses. The penalty of a miss is $180$ cycles. Cache hits do not produce any penalty.

a$)$ What is the real CPI of the architecture?

b$)$ What is the average memory access time $($AMAT$)$ of the architecture?