Problem 1 Consider the following assembly language code: IO: add SR3,SR1,SRO; ADD R3 R1 + RO 11: Iw SR2,200(SR1); /LDW R2- MEMIR1+100] 2: bez SR4,R2,Label lIf SR4 SR2 Go to Label1 13: sw R2, 100 (SR4): 14: sub SR9,SR3,SR2; SUB R9 R3-R2 15: add SR4,SR9.SR6; //ADD R4 = R9 + R6 16: addi SR2,SR1,12; 17: lw SR1, 200 (SR2) 18: 1w SR7,120(SR1); Consider a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The pipeline is the typical 5-stage IF. ID, EX, MEM, WB MIPS design. For the above code, complete the pipeline diagram below (instructions on the left, cycles on top) for the code. Insert the //STW MEMIR4 + 100]-R2 //ADDI R2 = Ri + 12; /LDW R7 MEMIRI+ 120]; IILDW R1 -MEMIR2+200] R1; characters IF, ID, EX, MEM, WB for each instruction in the boxes. Assume that there two level of bypassing, that the second half of the decode stage performs a read of source registers, and that the first half of the write-back stage writes to the register file. Label all data stalls (Draw an X in the box). Label all data forwards that the forwarding unit detects (arrow between the stages handing off the data and the stages receiving the data). (a) What is the final execution time of the code? The final execution time is cycles (b) Verify your answer in part (a)