Problem 1 Consider the following assembly language code: 10: add SR3,SR1,SRO; 11: lw SR2,200(SR1); 12: bez SR4,R2.Labell SR4-SR2 Go to Labell 13: sw R2, 100(SR4): 14: sub SR9,SR3,SR2 15: add SR4,SR9SR6: A 16: addi SR2,SR1,12; ADD R3 /STW MEMIR4+ 100]-R2 SUB R9-R3-R2 ADD R4-R9+R6 //ADDI R2# R1+ 12; MDw RI-NEMIR2-200] Ri; LDW R7-MEMIR1+120 SUBR9 R3-R2 17: IwSR 1, 200(SR2) ; 18: Iw SR7,120(SRI); a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The characters IF, ID, EX, MEM, WB for each instruction in the boxes Assume that there two levels in the box). Label all data forwards that the forwarding unit detects (arrow between the stages sthe typical S-stage IF, ID, EX, MEM, WB MIPS design. For the above code, complete code. Insert the the pipeline diagram below (instructions on the left, cycles on top) for the of bypassing, that the second half of the decode stase performs a read of source registers, and that the first half of the wri te-back stage writes to the register file. Label all data stalls (Draw an handing off the data and the stages receiving the data) (a) What is the final execution time of the code? The final execution time is cycles (b) Verify your answer in part (a) (c) Assuming that the timings for the five pipeline stages are the ones given in the ta below, find how long would it take to execute the code in part (a) and the respective 0) Using a single-cycled processor (ii) Using a pipelined processor