Problem $1$

Consider the following MIPS code.

$\backslash$begin$\{$tabular$\}\{$lll$\}$

IO: & Iw $\backslash$$s$3,0(\backslash$$s$2)$ & $\backslash$# LDW $\backslash$$s$3=$ M$[\backslash$$s$2+0]\backslash \backslash$

I$1$: & Iw $\backslash$$s$1,12(\backslash$$s$4)$ & $\backslash$#LDW $\backslash$$s$1=$ M$[\backslash$$s$1=$ M$[\backslash$$s$4+12]\backslash \backslash$

I$2$: & add $\backslash$$s$5,\backslash$$s$1,\backslash$$s$3$ & $\backslash$# ADD $\backslash$$s$5=\backslash$$s$1+\backslash$$s$3\backslash \backslash$

I$3$: & beq $\backslash$$s$6,\backslash$$s$7,$ L$1$ & $\backslash$# IF $(\backslash$$s$6=\backslash$$s$7)$ goto L$1\backslash \backslash$

I$4$: & sw $\backslash$$s$5,0(\backslash$$s$3)$ & $\backslash$#STW M$[\backslash$$ s$3+0]=\backslash$$s$5\backslash \backslash$

I$5$: L$1$: sw $\backslash$$s$5,12(\backslash$$s$4)$ & $\backslash$#STW M$[\backslash$$s$4+12]=\backslash$$s$5$

$\backslash$end$\{$tabular$\}$

$-$ In the absence of hazards, a new instruction can be fed to the pipeline every cycle.

How many cycles does this code take to complete? Use the table below.

Problem $1$

Consider the following MIPS code.

IO: Iw $s$3,0($$s$2)$ # LDW $s$3=$ M$[$$s$2+0]$ I$1$: Iw $s$1,12($$s$4)$ #LDW $s$1=$ M$[$$s$1=$ M$[$$s$4+12]$ I$2$: add $s$5,$$s$1,$$s$3$ # ADD $s$5=$ $s$1+$ $s$3$ I$3$: beq $s$6,$$s$7,$ L$1$ # IF $($$s$6=$ $s$7)$ goto L$1$ I$4$: sw $s$5,0($$s$3)$ #STW M$[$$ s$3+0]=$ $s$5$ I$5$: L$1$: sw $s$5,12($$s$4)$ #STW M$[$$s$4+12]=$ $s$5$

In the absence of hazards, a new instruction can be fed to the pipeline every cycle.

How many cycles does this code take to complete? Use the table below.

B$)$ Suppose that the MIPS processor with the $5-$stage pipeline from part A$).$ In addition, suppose that:

The instruction and data cache are split allowing the overlap of instruction fetch with read$/$write data to the cache

The pipeline has hazard detection and forwarding.

How many cycles does this code take to complete? Use the table below.

cycles

C$)$ Suppose now that the Execution stage of the pipeline is split into two stages E$1$ and E$2$ and that instruction $($ i$+1)$ cannot use E$1$ until instruction $($i$)$ released E$2,$ or more general E$1$ cannot be used again until

E$2$ is finished processing. Using the assumptions from part B$),$ how many cycles does this code take to complete? Use the table below.

PLEASE SOLVE PARTS A$,$ B$,$ AND C$.$ SPECIFY BOTH WHICH ROW AND COLUMN THE INSTRUCTION BELONGS IN$.$ i$.$e: WB $($T$4,$ I$0)$