Problem 2 160 pts] Design a Verilog code for a traffic light controller (finite state machine) which will be used at the location@ N. Union Blvd and Ranch Dr North Safeway West Ranch Dr East Primeri 4 South I/O Signa width input input outputnorth t [3:01 outpu output east[3:0] output west tl 3:0] clk reset Output description Left: 1000 Green: 0100 Yellow: 0010 Red: 0001 uth t (3:0] The controller will have two input signals (clk, reset) and four output signals (north tl, south tl, east tl west _tl) that are connected to each signal light. Each output has 4 bits (one-hot) and each bit will control Left (1000), Green (0100), Yellow (0010) and Red (0001) light as shown in above table One traffic signal will have four lights (left, green, yellow, red), but we will use only two states (* left green, * yellow) per a traffic signal for this design because left signal and green signal will be Problem 2 160 pts] Design a Verilog code for a traffic light controller (finite state machine) which will be used at the location@ N. Union Blvd and Ranch Dr North Safeway West Ranch Dr East Primeri 4 South I/O Signa width input input outputnorth t [3:01 outpu output east[3:0] output west tl 3:0] clk reset Output description Left: 1000 Green: 0100 Yellow: 0010 Red: 0001 uth t (3:0] The controller will have two input signals (clk, reset) and four output signals (north tl, south tl, east tl west _tl) that are connected to each signal light. Each output has 4 bits (one-hot) and each bit will control Left (1000), Green (0100), Yellow (0010) and Red (0001) light as shown in above table One traffic signal will have four lights (left, green, yellow, red), but we will use only two states (* left green, * yellow) per a traffic signal for this design because left signal and green signal will be