Problem $2.$

A$.$ Design the simplest dynamic CMOS logic gate that implements the function

$Y\frac{?}{b}=ar(A*(B)+BC+C*D+C)$

B$.$ Size the PDN for matching a reference inverter with $(\frac{W}{L}{)}_n=0\mathrm{.}27\frac{m}{0\mathrm{.}18}m$

C$.$ Knowing $V_{DD}=1\mathrm{.}8V,V_{tn}=-V_{tp}=0\mathrm{.}5V,{}_n{C}_{ox}=3{}_p{C}_{cx}=300\frac{A}{V^2}$ and the load capacitance $C{l}_L=20fF.$

i$.$ Design the Precharge PMOS transistor such that when $V_O=0\mathrm{.}1$ VDD the precharge current $I_p=190A.$

ii$.$ In a Precharge sequence, the output is initially zero. Calculate the rise time of the output voltage $($time for Vo to reach $0\mathrm{.}9$ VDD starting at $0\mathrm{.}1$ VDD $).$

iii. Determine the maximum allowed clock frequency knowing that the clock has to satisfy the following conditions :

a$.$ Remain ON during the output voltage rise time $($caculated in ii$.)$

b$.$ Remain OFF during the longest evaluation period of the Low state $(($:$2t_{pHL}$