Problem $2$: Adder Design $(28$ pts$)$

Consider a $24-$bit adder design based on the Carry$-$Bypass architecture. PG is the logic unit to produce $P$ and $G.$ Assume the following delays for each $1-$bit adder:

$,t_{PG}($delay to produce $P_i$ and $G_i$ signals from $A_i$ and $B_i)=4$

$,t_{\text{c}\text{a}\text{r}\text{r}\text{y}}($delay to compute $C_{\text{o}\text{u}\text{t},i}$ from $P_i,G_i$ and $($:$C_{in,i}$