Problem 2: Consider the Pentium memory system (Figure 1). PTEs and PDEs are 32 bits wide. 1. How many entries can the level-1 page table hold? 2. Assume there is a single task running on the system. The task's heap area is allocated in the physical range 0660000 - 0x666600. The task's stack area is allocated in the physical range 0799940008000000. The task's text area is allocated in the physical range 0100001400. The task has no other sections. (a) How many valid PTEs are there? (b) How many valid PDEs are there? (c) How much memory is in use strictly by the Page Directory and Page Tables? 3. If the Pentium used a flat page table, how much space would that page table take up? 4. The Pentium can overlap some of the translation of a virtual address with the cache lookup for that address. If Intel wants to preserve this behavior but also double the size of the cache, how must they change the cache? Figure 1: Summary of Pentium address translation)