Problem 2: GOAL: Understanding hazards and stalls in pipelining Assumeusing a simple n-order IF-ID-EX-MEM-WB pipeline MIPS processor. Show if there are any data hazard and stall. In the case of a data hazard, what forwarding path is activated? Circle the register(s) that cause the hazard. Example: ADD (r4) r6, r7 ADD r8, r8 Answer: i. Data hazard ii. No stall iii Forward WB to EXE a) ADD r7, r9, r10 SW r10, 4(r7) LW 7,4(r9) b) SW r4, 4(r6) LW r3, 8(r4) ADD r4, r6, r8 SW r4, 4(r3) ADD r5, r3, r2 d) LW r4, 8(r5) ADD r7, r5, r4 ADD r5, r8, r5 e) SUB r3. r3. 1 ADD r0, r0, 4 ADD rl, r0, r3