Problem 2: This problem consists of two questions (A & B) and considers the basic MIPS 5-stage pipeline (F, D, EX, M, WB) For this problem, you should assume that there is full forwarding.) Q1 Show how the instructions below proceed through the pipeline and indicate many stall cycles occur. You should assume the beq instruction is taken. Use the following chart. explain your working out (30 marks) lww $1, 0(52) add S2, $2, S2 sub S2, S2, 51 beq, $2, $2, lww $1, 4(52) X: add 52, S2, S1 Q2 Assume the following sequence of instructions is executed in a traditional 5-stage pipeline. Does the lw Iadd instruction combination represent a data hazard? If so, why? If not, why not? lw sub add $5, 4(6) $6, S5, S10 $7, $6, $5