Problem 3 (20 points). Imagine that you are a hardware designer who wants to add a new instruction to the MIPS ISA. Our ne instruction has the following syntax: lwr $rd, $rt(Srs) the load word register instruction, which loads a word from memory into a destination register using a register as an offset (convenien!). Assume that we have found a way of encoding this instruction into 32-bit machine code using the R-type encoding format. We now want to modify the single-cycle datapath in Figure 1 to support the execution of this instruction. 1. Which new blocks (if any) do we need to add to support execution of this instruction? Please describe briefly and draw a figure to reflect the new design. Your goal must be to make minimum modifications to existing hardware 2. What new control signals (if any) do we need from the control unit to support this instruction? 3. Write the values for following control signals as well as any new control signals added: RegDst, Jump, Branch, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite Problem 3 (20 points). Imagine that you are a hardware designer who wants to add a new instruction to the MIPS ISA. Our ne instruction has the following syntax: lwr $rd, $rt(Srs) the load word register instruction, which loads a word from memory into a destination register using a register as an offset (convenien!). Assume that we have found a way of encoding this instruction into 32-bit machine code using the R-type encoding format. We now want to modify the single-cycle datapath in Figure 1 to support the execution of this instruction. 1. Which new blocks (if any) do we need to add to support execution of this instruction? Please describe briefly and draw a figure to reflect the new design. Your goal must be to make minimum modifications to existing hardware 2. What new control signals (if any) do we need from the control unit to support this instruction? 3. Write the values for following control signals as well as any new control signals added: RegDst, Jump, Branch, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite