PROBLEM 3 (20 PTS) Periodic Pulse Generator: This system generates an active-high pulse (10 us) every 60 ms. 60 ms Periodic Pulse Generator S S 10 us ... Operation: The circuit starts generating the periodic pulse when the s signal (usually a one-cycle pulse) is asserted. Input: s (start signal). Outputs: p (60ms periodic pulse). Clock frequency: 100 MHz. Sketch the circuit: FSM + Datapath components. Specify all the I/Os of the FSM, as well as the signals connecting the FSM and the Datapath components (as in Problem 2). Suggestion: The Datapath only needs two counters (one for 60 ms and one for 10 us). You can use the parametric counter with enable and synchronous clear (my_genpulse_sclr). Counter Q: 10 us counter. For a clock period of 10 ns, it counts from 0 to 999. Counter R: 60 ms counter. For a clock period of 10 ns, it counts from 0 to 6x106 - 1. Provide the State Diagram (in ASM form) of the FSM. PROBLEM 3 (20 PTS) Periodic Pulse Generator: This system generates an active-high pulse (10 us) every 60 ms. 60 ms Periodic Pulse Generator S S 10 us ... Operation: The circuit starts generating the periodic pulse when the s signal (usually a one-cycle pulse) is asserted. Input: s (start signal). Outputs: p (60ms periodic pulse). Clock frequency: 100 MHz. Sketch the circuit: FSM + Datapath components. Specify all the I/Os of the FSM, as well as the signals connecting the FSM and the Datapath components (as in Problem 2). Suggestion: The Datapath only needs two counters (one for 60 ms and one for 10 us). You can use the parametric counter with enable and synchronous clear (my_genpulse_sclr). Counter Q: 10 us counter. For a clock period of 10 ns, it counts from 0 to 999. Counter R: 60 ms counter. For a clock period of 10 ns, it counts from 0 to 6x106 - 1. Provide the State Diagram (in ASM form) of the FSM