Problem #$3$: In the amplifier circuit below, assume the input voltages are equal and such that all transistors are in saturation. The transistor properties are as follows:

PMOS

$V_t=-0\mathrm{.}9V$

$V_t=+0\mathrm{.}8V$

$k_p^{\text{'}}=0\mathrm{.}07m\frac{A}{V^2}$

$=0\mathrm{.}01$

$V^{-1}$

$L=0\mathrm{.}8m$

NMOS

$k_n^{\text{'}}=0\mathrm{.}14m\frac{A}{V^2}$

$=0\mathrm{.}01V^{-1}$

$L=0\mathrm{.}8m$

For $Q1-Q8,W=8m.$ For $Q9-Q10,W=60m.$

$($a$)$ Assume $I_{D3}=300uA.$ Give the drain current for every other transistor in the circuit.

$($b$)$ What value of $R$ is required to obtain $I_{D3}=300uA?$

$($c$)$ Estimate the midband gain of each stage and the entire amplifier.

$($d$)$ Estimate the output impedance.

$($e$)$ Suppose a capacitor of value $35$ pF is connected from the drain of Q $8$ to the gate of Q $8,$ to intentionally create a single dominant pole. Estimate the high frequency cutoff.