Problem $4(20$ points$)$: The following sequences are implemented in a $5-$stage pipeline assuming separate IM and DMEM.

ADD R$5,$ R$2,$ R$1$

LW R$3,4($R$5)$

LW R$2,0($R$2)$

OR R$3,$ R$5,$ R$3$

SW R$3,0($R$5)$

I. Assume there is no forwarding in this pipeline processor. By drawing standard pipelined diagram, indicate hazard by adding stalls $($if any$)$ to the diagram.

II$.$ Assume there is full forwarding in this pipeline processor. By drawing standard pipelined diagram, indicate hazard by adding stalls $($if any$)$ to the diagram.

III. If there is no separate memory for instruction and data, then will there be any structural hazard for part I? If yes then show by pipeline diagram, how to remove the hazard for part I.Appendix: