Problem 4: A truth table for a two-to-four decoder with enable input is given below: . D2 1 1 D3 1 1 1 0 O 0 0 0 0 1 1 0 1 0 1 DO 1 0 1 1 1 D1 1 1 0 1 1 1 1 0 1 0 This circuit operates with complemented outputs and a complement enable input. The decoder is enabled when E is equal to 0. As indicated in the table, one output can be 0 at any time. a) Write an entity declaration for this decoder. b) Write architecture body named decoder_select for this decoder using selected signal assignment statement. c) Write architecture body named decoder_case for this decoder using case statement. d) Using one instance of decoder_select and one instance of decoder_case design a three-to-eight. Draw a block diagram for this circuit. e) Write a structural VHLD (both entity declaration and architecture body) for the three-to-eight decoder. Note: The outputs of three-to-eight decoder are complemented as well. You do not need to implement enable signal on three-to-eight decoder. Problem 4: A truth table for a two-to-four decoder with enable input is given below: . D2 1 1 D3 1 1 1 0 O 0 0 0 0 1 1 0 1 0 1 DO 1 0 1 1 1 D1 1 1 0 1 1 1 1 0 1 0 This circuit operates with complemented outputs and a complement enable input. The decoder is enabled when E is equal to 0. As indicated in the table, one output can be 0 at any time. a) Write an entity declaration for this decoder. b) Write architecture body named decoder_select for this decoder using selected signal assignment statement. c) Write architecture body named decoder_case for this decoder using case statement. d) Using one instance of decoder_select and one instance of decoder_case design a three-to-eight. Draw a block diagram for this circuit. e) Write a structural VHLD (both entity declaration and architecture body) for the three-to-eight decoder. Note: The outputs of three-to-eight decoder are complemented as well. You do not need to implement enable signal on three-to-eight decoder