Problem $6.1$ Mealy finite state machine $($FSM$)$ is shown in figure $6\mathrm{.}4.$ This FSM uses one$-$hot

state encoding, S$\_(0)=001,$S$\_(1)=010,$ and S$\_(2)=100.$ The input is x$\_($in $)$ and the output is Y$\_($out $).$

Figure $6\mathrm{.}4.$ FSM machine for problem $5.$

Assume the hardware implementing this state machine includes the capability for scan testing.

The state register is constructed from D$-$type flip$-$flops with multiplexers selecting the input. The

multiplexers are controlled by a norma$($l$)/($s$)$can signal. The state register acts normally when this

signal is $0$ but is configured as a shift register when it is $1.$ Input SDI is the serial input for the

test data which is clocked in msb first, output SDO is used to output the results of a test.

Suppose we want to test all the transitions out of state S$\_(1)$ starting with S$\_(1)->$S$\_(0).$ Show

how this test would be done using a minimum number of clock cycles. Indicate the value of x$\_($in$),$

$()/($bar$)($ normal $()/($scan$),$SDI, and SDO for each clock cycle. Don't cares or unknown signals are marked $)$

with x$.$