Problem A. Assuming that there is no structure hazard in the parallel execution of two different stages, please identify (1) the type of hazard (Structure hazard, Data hazard, or Control hazard) and (2) in which stage of the 2^nd instruction such hazard occurs in the pipelined implementation of two instructions.

(b)	LDR R1, [R3, R6]	;its executed in five stages: IF, ID, EX, MEM, WB
	SUB R4, R8, #5	;its executed in four stages: IF, ID, EX, WB, there is only one Registers block