Problem A. Assuming that there is no structure hazard in the parallel execution of two different stages, please identify (1) the type of hazard (Structure hazard, Data hazard, or Control hazard) and (2) in which stage of the 2^nd instruction such hazard occurs in the pipelined implementation of two instructions.

(a) LOOP

BNE LOOP ;its executed in 3 stages: IF, ID, EX, CPU knows whether NE is true at the end of EX

ORR R7, R9, #5

;its executed in four stages: IF, ID, EX, WB