Processor C has a memory system with the following specifications: Memory Access Time $($in clock cycles$)$ Instruction Cache Data Cache Hit Rate Hit Rate $98\%94\%$ L$1$ Cache $1$ Main Memory $90$ The processor executes a program in which $38\%$ of the instructions contain data references. The base CPI of processor C is $1\mathrm{.}5.($a$)$ What is the miss penalty associated with fetching instructions? Specify in clock cycles per instruction. Miss penalty for fetching instructions $=[$a$]$ clock cycles per instruction $($b$)$ What is the miss penalty associated with reading and writing data? Specify in clock cycles per instruction. Miss penalty for reading and writing data $=[$b$]$ clock cycles per instruction. $($c$)$ What is the EFFECTIVE Clock Cycles per Instruction $($CPI EFF$)?$ CPI EFF $=[$c$]$ clock cycles per instruction. $($d$)$ Determine the speedup $($n$)$ if the L$1$ cache, specified above, is replaced by an ideal cache. Note: An ideal cache has a hit rate of $100\%.$ Speedup $($n$)=[$d$]$