Processor failures in a SMP system must be taken care by:

a.) Hardware

b.) Memory

c.) Operating System

d.) Compiler

Cache coherency is addressed in:

a.) Control Unit

b.) Hardware

c.) Software

d.) None of the above

This takes care of scheduling and synchronization between multiple processors:

a.) Control Unit

b.) Hardwired Control

c.) Operating System

d.) All of the above

Compared the CISC, RISC architecture has:

a.) Simpler Opcode

b.) Simple Addressing Modes

c.) Fewer Load/Store

d.) All of the Above

The main goal of compiler based register optimization is:

a.) Minimize Load/Store

b.) Minimize register Space

c.) Maximize register utilization

d.) None of the above