Project description:

In this project, we need to upgrade our accumulator computer described and implemented in the bit more complicated computer. The memory in this computer system is $16-$bit cell memory wi $($i$.$e$.$ cell width $=16$ bits$).$ The memory is synchronous to the CPU, and the CPU can read$/$v single clock cycle. The memory can only be accessed through the memory address registe memory buffer register $($MBR$).$

The CPU has a program counter $($PC$)$ register and an instruction register $($IR$).$ This CPU $1$ general$-$purpose registers $R0-$R$7.|$

The $16-$bit instruction format is as follow:

$\backslash$table$[[$Opcode$(3$bits$),$Dst$.$ Register $(3$bits$),$mode $(2$bits$),$Src$.$ Register$/$ Memory Address $(8!]]$

Addressing Modes bits for the last field of the instruction $(8$bits$)$:

$00=>$ Direct memory address

$01=>$ Register

$10=>$ Register Indirect

$11=>$ Constant

The opcodes are:

$000$ LOAD Ri$,$ operand: loads register Ri with a memory cell of address operand$/$register conten memory cell of address in register operand$/$or a constant integer operand.

$001$ STORE Ri$,[$M$]$: Stores the contents of Ri in memory cell of address M$.($only mode$=00$ is instruction$)$

$010$ ADD Ri$,$ operand: Adds the contents of Ri to the operand, and store the result in Ri$.$

$011$ SUB Ri$,$ M: subtract the contents operand from $Ri$ and store the result in $Ri.$