Provide the solutions

d. The Intel 80486 has an on-chip, unified cache. It contains 8 Kbytes and has a four-way set-associative organization and a block length of four 32 bit words. The cache is organised into 128 sets. There is a single "line valid bie" and three biits, BO, BI, and B2 (the "LREI" bit) per line. On a cache miss, the 80486 reads a 16-byte line from main memory in a bus memory read borst. Daw a simplified diagram of the cache and show how the different fields of the address are interpreted. (4 marks) e. Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain, in bytes/s? To increase its performance, would it be better to make its extemaldam bus 32 bits or to double the external clock frequency supplied to the microprocessori State any other assumptions you make, and explain. Hint Determine the number of bytes that can be transferred per bus cycle (4 marks)