Provided to you is a SystemVerilog procedural block.

$```$

always$\_$comb begin

y$1\_$o $=0$;

if $($en$\_$i$)$ begin

yO$\_$o $=$ x$0\_$i;

y$1\_$o $=$ x$1\_$q;

end

end

$```$

Answer the following multiple choice questions according to the "lowRISC Verilog Coding Style Guide" and the "IEEE $1800-2023$ SystemVerilog Standard Section $9\mathrm{.}2\mathrm{.}2\mathrm{.}2".$

$1.$ The $\_$q suffix denotes that x $1$ q is a

a$.$ internal net.

b$.$ input.

c$.$ output.

d$.$ flip$-$flop input.

e$.$ flip$-$flop output.

$2.$ The $\_$o suffix denotes that y$0\_$o and y$1\_$o are

a$.$ internal nets.

b$.$ inputs.

c$.$ outputs.

d$.$ flip$-$flop inputs.

e$.$ flip$-$flop outputs.

$3.$ The procedural block will produce the following:

a$.$ A MUX$2$ that drives y$0\_$o and a MUX$2$ that drives y$1\_$o$.$

b$.$ A MUX$2$ that drives xo$\_$i and a MUX$2$ that drives x$1\_$i$.$

c$.$ A MUX$2$ that drives y$1\_$o and a Latch that drives y$0\_$o$.$

d$.$ A warning$/$error message that a latch is inferred.

$4.$ What if any changes are required to ensure the behavior of this procedural block produces purely combinational logic?

a$.$ No changes needed.

b$.$ y$1\_$o should not be set to $0$ at the top of the procedural block.

c$.$ y$0\_$o should be set to $0$ at the top of the procedural block.

d$.$ The if statement should be removed because if statements cannot produce combinational logic.