Purpose:

To write a VHDL code for a simple 4-bit BCD counter

To write a VHDL code for a seven segment decoder

To write a vhdl code to tie the designs above to update and display a count from 00 to 59.

To synthesize, implement, program and test the design on the ALTERA Cyclone IVE chip

Equipment:

PC with ALTERA Quartus II Tools, DE2-115 board.

Discussion:

We have seen how JK flip-flops can be used as building blocks to implement counters. In this lab, a counter is described in behavioral mode to count from 00-59 with clock pulses as follows:

Counter Module:

This module is used twice, once to update the ones count and again to update the tens count.

Updating the ones:

In this process, when the asynchronous input reset is activated or the counter reaches a count STOP=10, the counter output Q is cleared. When the counter is enabled, a clock pulse from the push button KEY(0) will update the count from 0 to 9. A second process simply allows the tens counter to wake up (=1) for one clock pulse at the STOP count of 10 before it goes back to sleep (=0).

Updating the tens:

The only difference between implementing the ones and the tens is that the tens STOP is now 6. To this end, STOP is declared as generic and will be assigned a value of 10 or 6 in the TIE module.

Notice that either count is cleared at 10 or 6 at the edge of the clock pulse.

Seven Segment Module:

The seven segment module is similar to the one used in previous labs and uses a Truth Table description starting with the withselect construct.

Tie Module:

Finally, a TIE module is used to tie the design to the outside world made of a clock KEY(0) and a reset SW(0) at the input and HEX0 and HEX1 for the display at the output.

See Figure 1 below.

Notice that wires labeled rope1, rope2, rope3 are needed to complete the connections between modules. There is no need to have wires to connect to the outside world.

Figure 1. Counter 00-59

Procedure: PART A

Open a project, call it countdisp.

Open a VHDL file then copy and paste the code for a counter. Complete the code by filling in the blanks,

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity count is

generic(stop: std_logic_vector(3 downto 0));--STOP is declared as generic

port (_________________________________;

wake_up : ____________________________;

Q : ___________________________________________);--use buffer for mode end count;

architecture Behavioral of count is

begin

wake_up_0:--check for clear or update count

process(___________________________)--sensitivity list

begin

if ___________or Q=______ then check for active reset or terminal count

Q<=_______________; --clear output

wake_up<=__________; --if yes, wake up

elsif enable=______ then --otherwise check for active enable

if __________________ then --if so, update count on the rising edge of clk.

Q<=______________;

wake_up=________;--else keep it in sleep mode

end if;

end if;

end process;

end Behavioral;

Save file as counter.

PART B

Open a new VHDL file.

Copy and paste then complete the seven segment decoder VHDL code below:

LIBRARY ieee; 

use ieee.std_logic_1164.ALL; 

use ieee.std_logic_arith.all; 

use ieee.std_logic_unsigned.all; 

ENTITY seven IS 

port 

( _______________________________; 

 _______________________________ 

); 

END seven; 

architecture Behavioral of seven is

begin

with ________ select ________<=

"________" when "0000", --0

"________" when "0001", --1

"________" when "0010", --2

"________"when "0011", --3

"________"when "0100", --4

"________"when "0101", --5

"________"when "0110", --6

"________"when "0111", --7

"________"when "1000", --8

"________"when "1001", --9

"________"when "1010"|"1011"|"1100"|"1101"|"1110"|"1111", --Display E for error

"________"when others;

end Behavioral;

Save it as seven.

PART C

Open a new VHDL file.

Copy, paste then use the diagram of Figure 1 above to describe the entity and the architecture of the instantiation code to tie the two designs: Seven.vhd and Counter.vhd together.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CountDisp is

(___________________________________;--in are SW and KEY

___________________________________;--out is HEX0

___________________________________);--out is HEX1

end CountDisp;

architecture Behavioral of CountDisp is --Declare signals

begin

A1: --see Figure 1

entity work.count (behavioral);

generic map ("________");--binary value 10 for STOP

port map (reset=>__________, wake_up=>________, enable=>________, clk=>_________, Q=>__________);

A2: --see Figure 1

entity work.count (behavioral);

generic map ("________");--binary value 6 for STOP

port map (reset=>__________, wake_up=>________, enable=>________, clk=>_________, Q=>__________);

A3: --see Figure 1

entity work.seven (behavioral);

port map (DS=>__________, SS=>_________);

A4:--see Figure 1

entity work.seven (behavioral);

port map (DS=>__________, SS=>_________);

end Behavioral;

Save it as CountDisp.

Part D:

Compile, import pin assignment, burn then test the design.