Q$1)30$ points $(5+15+10)$

The following circuits shows $4-$bit Synchronous Counter with enable and asynchronous clear $($reset$).$ We want to build generic version of this counter structurally.

a$.$ Write a Verilog description for T$-$FF with asynchronous reset.

b$.$ Use the T$-$FF in part $($a$)$ to write a Verilog description for a GENERIC n$-$bit counter.

c$.$ Write a test$-$bench for n$=3($the test bench should include different cases and print inputs$/$outputs$).$

a$.$ For the following state diagram. An Asynchronous rest takes the state to $"00".$ Write a Verilog description for this circuit.

b$.$ Write a UDP description for a negative edge D Flip Flop. Q$1)30$ points $\backslash ((5+15+10)\backslash )$

The following circuits shows $4-$bit Synchronous Counter with enable and asynchronous clear $($reset$).$ We want to build generic version of this counter structurally.

a$.$ Write a Verilog description for T$-$FF with asynchronous reset.

b$.$ Use the T$-$FF in part $($a$)$ to write a Verilog description for a GENERIC n$-$bit counter.

c$.$ Write a test$-$bench for $\backslash (\backslash$mathrm$\{$n$\}=3\backslash )($the test bench should include different cases and print inputs$/$outputs$).$

Q$2)20$ points $\backslash ((\backslash$mathbf$\{12+8\})\backslash )$

a$.$ For the following state diagram. An Asynchronous rest takes the state to $"00".$ Write a Verilog description for this circuit.

b$.$ Write a UDP description for a negative edge D Flip Flop.