Q$1[40$ Points$].$ For a daisy$-$chained SPI with $4$ devices Device #$1$ Device #$2$ Device #$3$ Device #$4),$ the SPI master intends to send the following bytes to the devices in sequence:

$0$x$5$A to Device #$1$

$0$x$6$B to Device #$2$

$0$x$7$C to Device #$3$

$0$x$8$D to Device #$4$

Additionally, at the start of communication, all devices hold the byte $0$xFF in their SPI shift registers.

$($Part $1)$ After $32$ clock cycles, what will be the contents of the SPI shift registers of devices?

$($Part $2)$ If the SPI clock operates at $500$ kHz $,$ how long $($in milliseconds$)$ will it take for the SPI master to complete the transmission to all devices and receive back the first byte sent?

$($Part $3)$ Suppose the master sends the byte sequence with an incorrect clock frequency of $250$ kHz $,$ but the devices expect $500$ kHz $.$ What would be the potential impact on the data received by Device #$4,$ and why?

$($Part $4)$ If Device #$2$ is configured to reverse the bits of the data it receives before passing it on$,$ what will be the final byte received by the master after $32$ clock cycles?