Q$1$: Design a Half Adder using NAND Gates only:

Step$1$: Understanding the Half Adder Function:

Carry $=$AB Sum $=($A$)/($b$)$ar $($B$)(+)/($b$)$ar $($A$)$B

$,=$Ao$+$B

Step$2$: Changing the gates to Nand gate.

Step$3$: Draw the logic diagram.

Q$2$: Giving a $3-$bit binary up$-$counter using T flip$-$flops.

Provide the waveform diagram for the clock signal,

showing at least four complete cycles. Clearly indicate

the rising or falling edges of the clock signal and also the

values for each duty cycle.