Q$2$:

Design a $3-$bit up$-$counter which increments by one normally, and increments by two every other clock cycle, e$.$g$.$ the starting sequence of your counter should be as follows, $\backslash (000,001,011,100,110,\backslash$ldots $\backslash )$

You may use any number of $1-$bit half or full adders, $1-$bit multi$-$function registers, any$-$bit multiplexors and logical gates. There should be an input for the clock and an input clr which resets the counter to $0$ when clr $\backslash (=1\backslash ).$ There should be $3-$bits of output which represents the current count and an output tc that is $1$ when the counter is at its terminal count.