The following algorithm is used to find the integer square root for an input integer number X $[$Ex$1$: if X $\{4,5,6,7,8\},$ then the result integer square root Y $=2][$Ex$2$: if X $\{9,10,11,12,13,14,15\},$ then the result integer square root Y $=3]$Input: X $($n$-$bit integer number$)$Output: Y$=$ VXStep$1$: Initialization: $4=$X Imput Data$)$Q$=1$B $=3$step$2$: Q $=$ Q $+$ Bstep$3$: B $=$ B $+2$repeat the last two steps $($step $2$ and step $3)$ until Q $>$ A step$4$: Shift B one bit to the right $($a logical shift$)$step$5$: Y $=$ B$-1($The result$)$Complete the following Verilog code to provide a behavioral implementation for this algorithm. module SORT$\_$Calculator $($input CLK$,$ input $[9$:$0]$ x$,$ output reg $[4$:$0]$ YYour design should include the following pins:$1.$ CLK: $($negative edge trigger input clock$)2.$ X: The input number $(10$ bits$)3.$ Y: The result square root $(5$ bits$)($Hint: define the variables A$,$ B$,$ and Q to be of size $11)$Notes:: she sens descrieDO NOT use the following operators: $/,*,\%$ DO NOT use an algorithmic state machine.The calculation should be synchronous with the clock $($the result should be calculated in a single clock cycle at the falling edge of the input clock$)$You have to use EDA Playground for this assignmentYou have to submit two files:$1.$ A Verilog code to implement your Design$\mathrm{.}2.$ A testbench file to simulate and test your design:a$.$ Set the clock period to be $2$ns$.$b$.$ You have to cover all the possible cases for the input data $(1024$ different cases$)$c$.$ For each case you have to:i$.$ Select the value for X $($from $0$ to $1023)$ ii$.$ Wait for two clock cycles