Q$2-$ Signed arithmetic $-$ Y $=$ mx $+$ c and Pipelining

Design and implement a verilog module called $$line$$ as per the following specification.

Top level

Port name

Direction Width Description

rst$\_$n Input $0$:$0$ Active low reset

clk Input $0$:$0$ Clock

m Input $3$:$0$ Signed input

x Input $3$:$0$ Signed input

c Input $3$:$0$ Signed input

valid$\_$in input $0$:$0$ Inputs valid

y Output $7$:$0$ Signed output

y$\_$valid Output $0$:$0$ Y valid, driven by design

The module should carry out the complete calculation in $2$ stages $(1$ clock per stage$)-$

The first stage should calculate the product $($m$*$x$)$ and the second stage should calculate the sum

$($product $+$ c$).$ These stages are not balanced, but we will live with it for now. In order to balance

the stages, one option would be to pipeline the multiplier itself as well.

You may use the multiplier and adder from the IP catalog or just use $*$ and $+$ verilog operators.