Question: Q 3 ( 2 0 % ) Complete the following diagram. All Q outputs start with zero. Note: There is certain delay in each

Q3(20\%) Complete the following diagram. All Q outputs start with zero.
Note: There is certain delay in each DFF!
Thus Q2 cannot get Q1's values in the same clock cycle! It must wait for one more clock cycle. That's why it is called "shift register"!
Q 3 ( 2 0 \ % ) Complete the following diagram.

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