Q$3$: The following VHDL codes realize the Boolean equation $"F=x$ and $Y"$ in three different ways.

They were labeled F$1,$ F$2,$ and F$3.$ Explain the differences between these three descriptions$/$circuits$.$

library IEEE;

use IEEE.std$\_$logic$\_1164.$all;

entity hw$3$ is

port $($

clock, reset: in std$\_$logic;

$x,Y$: in std$\_$logic;

F$1,$ F$2,$ F$3$: out std$\_$logic

;

end hw$3$;

architecture DE$1\_$SoC of hw$3$ is

begin

$F1x$ and $Y$;

hw$3\_$demo: process $($clock$,$ reset$)$

begin

if $($reset $={?}^{\text{'}}0\text{'})$ then

$F2x$ and $Y$;

F;

elsif rising$\_$edge$($clock$)$ then

$F3\stackrel{}{x}$ and $Y$;

end if;

end process;

end architecture DE$1\_$SoC;