Q$4$ A basic adder in a $4-$bit CPU is shown in Fig$\mathrm{.}4-1,$ where the $\text{'}1-$bit FA$\text{'}$ is a $1-$bit full adder and the $\text{'}4-$bit data storage' is a $4-$bit shift register.

$[25]$

$($a$)$ Briefly describe the function of the $5$ submodules in Fig$\mathrm{.}4-1$ as much as possible. $[5]$

$($b$)$ The timing specification of the submodule is listed in Table $4-1.$

$\backslash$table$[[$D Latch,Propagation delay $t_{pd}$ :$,$Max$=12$ns$,$ Min$=8$ns$],[$D Flip$-$Flop,Propagation delay tpri:,Max$=22$ns$,,$ Min$=18$ns$],[$Setup time $t_{\text{s}\text{e}\text{l}\text{u}\text{p}}$ :$,$Max$=7$ns$,$ Min$=5$ns$],[1-$bit FA$,$Propagation delay $t_{\text{P}\text{F}\text{A}}$ :$,$Max$=40$ns$,$ Min$=25$ns$]]$

Table $4-1$

i$)$ Analyze the highest frequency of the clock $(f_{CLK}).$

$[2]$

ii$)$ If we want to get a higher performance $($i$.$e$.$ faster$)$ adder, how should we change the design in Fig$\mathrm{.}4-1?$ Briefly describe your ideas.

$($c$)$ Compose an HDL code for this adder, with all necessary notes. Assume the $4$bit shift register is already implemented as:

$[8]$

module ShiftReg $($ input data,

input clk$,$

output datai $)$;

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Continued overleaf

$($d$)$ Compose a simple testbench in HDL for this adder, with all necessary notes. $[8]$