Q$.4($a$)$ The configurable logic block of FPGA can be configured to work as a function generator or as a memory block. The figure shows the internal architecture of a Xilinx CLB$.$ Show how you can use this block to implement two $\backslash (16\backslash$times $1\backslash )$ SRAMs and one $\backslash (32\backslash$times $1\backslash )$ SRAM. Highlight and mention all the control signals and gates that would be used to implement them.

Q$.4($b$)$ The task is to implement a $\backslash (32\backslash$mathrm$\{$~K$\}\backslash$times $32\backslash )$ memory. Assume you are given $32$ Kbit configurable memory blocks such as a block RAM in an FPGA. Each block can be configured as a $\backslash (32\backslash$mathrm$\{$~K$\}\backslash$times $1\backslash )$ bit memory or a $\backslash (1\backslash$mathrm$\{$~K$\}\backslash$times $32\backslash )$ bit memory. Which option would you choose as a building block for your $\backslash (32\backslash$mathrm$\{$~K$\}$ x $32\backslash )$ bit memory and why?

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$[5+5=10]$

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