Q$4)$ Con

of data path $($IF$,$ D$/$R$,$ ALU, DM$,$ WB$.$ Also assume that writing into aregistethrehcalopcpkencsycnile.thAelsofi,rsatsshuamlfe tha clock cycle while reading from aregister happens ni thesecond shpalrfeodficttaken$)$ tofetch the instruction the hardware wil apply "predicted$-$ taken"predictor $($i$.$e$.$ alway

takes twocycles as after the branch and flush it later ni case of misprediction. Also, assume branch

did in class.

Loop:

Iw

St$9,0($St$8)$

#I$1$; Load from location $(1000)$ addi

$$9,$ St$9,-1$

#$12$

SW

St$9,$ O$($St$8)$

#$13$

addi

St$8,$St$8,8$ #$14$

addi

St$1,$ $t$1,-1$

#$15$; $t$1$ initiallycontains $1($one$)$ one

$t$1,$ $zero, Loop #$16$

SW

St$9,0($$t$8)$

#$17$

$1000$

A

$1008$

C

$($a$)$ List the read$-$after$-$write data dependencies. As an example, x on y $($$$5)$ shows instruction x has d dependency oninstruction ysince it is reading register $$5.$

$($b$)$Assume the $5-$stage MIPS pipelinewith no forwarding,what is the total number ofstall cycles?W si the execution time $($in cycles$)$ for the whole program? Showyour work.

$($c$)$ Assumethe$5-$stageMIPSpipelinewithfull forw

si theexecution time $($incycles$)$ for th arding, what is the total number

e whole program?Show yourwork. of stall cycles?