Q$4$: Design a one$-$input, one$-$output serial $2$s complementor. The circuit accepts a string of

bits from the input and generates the $2$s complement at the output. The circuit can be

reset asynchronously to start and end the operation.

Test your circuit using the following input sequence.

$1)010111110111100$

$2)$ Random sequence of your choice

Requirements:

$1.$ Draw the state table and diagram the circuit should still working until active low reset is activated

$2.$ Write a Verilog design code and test bench for the previous program which accept a serial data input and generates its $2$s complement note that the size of input is not known