Q$4.$ Write a program to simulate the process of address translation using a two level

page table with a page directory for virtual memory management. $[20$ pts$]$

Design :

$$ Implement a two$-$level page table structure. The first level is a Page Directory

$($PD$)$ which points to the Page Tables.

$$ Assume that a virtual address is divided into three parts

$$ Page Directory Index $(10$ bits$)$: Top level index that maps to an entry in the

Page Directory.

$$ Page Table Index $(10$ bits$)$: Second level index that maps to an entry in the

page table.

$$ Offset $(12$ bits$)$: Offset within the actual page

$$ Use the following configuration

$$ Virtual Address Length: $32$bit $($ Eg : $0$xCCC$0$FFEE$)$

$$ Page Size: $4$KB

$$ Page Table Entries: Each page table has $1024$ entries $($each entry is of

$4$B$).$

$$ Address Translation:

$$ Implement an API consisting of two functions, load and store with the

following signature as shown below.

uint$8\_$t load$($uint$32\_$t va$)\{$

assert$(0$ && $$TODO : SIMULATE READING FROM va$)$;

$\}$

void store$($uint$32\_$t va$)\{$

assert$(0$ && $$TODO : SIMULATE WRITING INTO va$)$;

$\}$

$$ Implement these functions to simulate memory access. If the address can

be successfully translated to a physical address, then load$/$store the value

into the physical address. If the address cannot be translated i$.$e$.,$ PD or

Page Table Entry is invalid $($null$),$ simulate a page fault and update the PD

and Page Tables accordingly.

Deliverables:

$$ Hook into your load and store API$$s to track and display the total number of page

hits and page misses.

$$ The page table and the page directory size.

$$ For page misses, show the updates made to the PD and Page Table.

$$ Provide a summary at the end showing the hit$/$miss ratio.