Q$5(10$ points$)$: Memory consistency

Two threads $($ A and B $)$ are concurrently running on a dual$-$core processor that implements a sequentially consistent memory model. Assume that the value at address $($R$10)$ is initialized to $0.$ The instruction st immediate, $($R$10)$ writes an immediate number into the memory address stored in R$10.$

After both threads have finished executing, you find that $\backslash (($R $1,$ R $2,$ R $3,$ R $4)=(1,2,3,4)\backslash ).$ How many different instruction orderings of the two threads produce this result $($please show all possible orderings$)?$