Question: Q 6 Suppose that in 1 0 0 0 memory references there are 6 0 misses in the first level cache and 3 0 misses

Q6 Suppose that in 1000 memory references there are 60 misses in the first level cache and 30 misses in the second-level cache.
(a)\{2 marks \(\}\) What are the local miss rate and global miss rate of each cache?
(b)\{3 marks \} Assume the miss penalty from the L2 cache to memory is 180 clock cycles, the hit time of the L2 cache is 8 clock cycle, the hit time of L1 is 1 clock cycle. What is the average memory access time? (ignore the impact of writes)
(c)\{3 marks\} What would be the average memory access time if we just have the L1 cache (i.e., we remove the L2 cache)? Note that the penalty of L1 in this case will be 180 clock cycles.
Q 6 Suppose that in 1 0 0 0 memory references

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