Q1. Design a modified D flip-flop that changes state on rising edges of the clock input, when enable input (E) is ' 1 '. It has a reset input, R. When R=1 ', it resets the flip-flop output to Q= ' 0 ' independent of the clock and enable input. Similarly, it has a set input, S, that sets the flip-flop to ' 1 ' when S= ' 1 ' on the clock rising edge, but independent of E. Write a VHDL description of this modified D flip-flop