Q1: Vector Architecture Consider the following loop:

for (i=0; i<64; i++)

X[i] = a * X[i] + b; Here is the assembly code for the loop. Assume that prior to the loop, i is in R1, 64*4 is in R2, a is in F0, and b is in F2.

I0: ld F4, X(R1)

I1: mul F4, F4, F0

I2: add F4, F4, F2

I3: st F4, X(R1)

I4: addi R1, R1, #4

I5: bne R1, R2, I0

Consider a processor with 32-element vector processor. The processor has four fully-pipelined vector execution units: a 2-cycle load unit, a 2-cycle store unit, a 2- cycle FP adder, and a 4-cycle FP multiplier. A) The vector processor does not supports chaining. How long would it take the original loop to execute on this processor? You ignore overlaps between multiple vector chains and the scalar code for setting up each group of vector operations.

B) Let assume that the vector processor supports chaining. How long would it take the original loop to execute on this processor?

( Please answer as numbers and digram for cycle NOT coding ) for subject ( 468 - Computer Architecture ) ( Chapter 6 (section 6.1 - 6.5) )