Q2. Consider a 4-way set associative cache. Suppose that the 3 pseudo-LRU bits for set 7 are 001 and the set is currently full. The next memory reference that maps to set 7 is a write miss. The pseudo-LRU bits are described in module 9 material.

a) (5) Assuming a write-allocate policy is used, which line (way0, way1, way2 or way3) within set 7 should be replaced in response to the write miss?

b) (5) Suppose that the reference to set 7 had instead caused a hit in way2, and that the three pseudo-LRU bits for set 7 were 001 before the reference. What would the three pseudo-LRU bits be after the reference is made?