Q3. Consider a computer that uses 36 bits long virtual addresses and 16KB long pages. The computer has 4 GB RAM (main/physical memory). The physical addresses are also 36 bits long. A page table entry (no matter what kind of a page table it is in) is 8 bytes long. We have 2 processes in the system with the following logical memory layouts (dark areas are used): a) What is the memory (RAM) space required to hold all page table information for these two processes if single level page table scheme is used. b) What is the memory space required to hold all page table information for these two processes if two level page table scheme is used with the following address partitioning: 11 bits for p1,11 bits for p2,14 bits for offset (i.e., 11,11,14)? c) What is the memory space required to hold all page table information for these two processes if inverted page table scheme is used (ignore chaining effects)