Question: Q(4) Consider, a processor with dynamic scheduling using Tomasulu algorithm. For the code segment given below, show what the status table looks like when the

Q(4) Consider, a processor with dynamic scheduling using Tomasulu algorithm. For

Q(4) Consider, a processor with dynamic scheduling using Tomasulu algorithm. For the code segment given below, show what the status table looks like when the Div.d has written its results. The latency of instructions is as follows: load 1 cycle, add 2 cycles, sub 2 cycles, mult 6 cycles and div 12 cycles. L.D L.D FMULT.D f.SUB FDIV.D FADD.D F2, 44(R1) F6, 32R1) FO, F2, F4 F8, F2, F6 FO, FO, F6 F6, F8, F2 Instruction Issue (cycle) Execute (cycle) Write(cycle)

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