Q5 (12 points) Cache Memory Parameters = A 4-way set-associative cache has a capacity of 256 KiB (1 KiB = 1024 bytes) and each cache block consists of 64 Bytes. Each memory address consists of 32 bits. The cache uses the write- back policy and the FIFO replacement policy. a) (2 points) What is the total number of blocks in the cache? b) (1 point) What is the total number of sets in the cache? c) (1 point) How many bits in the memory address are used as a byte offset within a block? d) (1 point) How many bits in the memory address are used to index a set in the cache? e) (1 point) How many bits in the memory address are used for the tag? f) (2 points) What is the number of valid and modified bits stored in the cache memory? g) (1 point) What is the total number of tag bits stored in the cache memory? h) (1 point) How many comparators are used for tag comparison in the cache memory? i) (1 point) How many bits in the cache memory are needed for the FIFO replacement policy? j) (1 point) If the replacement policy is changed to random, how many bits are needed for random replacement in the entire cache memory