As described in Section 5.7, virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitutes a stream of virtual addresses as seen on a system. Assume 4 KiB pages, a 4-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number.
4669, 2227, 13916, 34587, 48870, 12608, 49225
TLB

Valid .................................Physical Page or in Disk
1 .........................................................5
0 .........................................................Disk
0 .........................................................Disk
1 .........................................................6
1 .........................................................9
1 .........................................................11
0 .........................................................Disk
1 .........................................................4
0 .........................................................Disk
0 .........................................................Disk
1 .........................................................3
1 .........................................................12

1. Given the address stream shown, and the initial TLB and page table states provided above, show the final state of the system. Also list for each reference if it is a hit in the TLB, a hit in the page table, or a page fault.

2. Repeat 5.11.1, but this time use 16 KiB pages instead of 4 KiB pages. What would be some of the advantages of having a larger page size? What are some of the disadvantages?

3. Show the final contents of the TLB if it is 2-way set associative. Also show the contents of the TLB if it is direct mapped. Discuss the importance of having a TLB to high performance. How would virtual memory accesses be handled if there were no TLB?

There are several parameters that impact the overall size of the page table. Listed below are key page table parameters.

4. Given the parameters shown above, calculate the total page table size for a system running 5 applications that utilize half of the memory available.

5. Given the parameters shown above, calculate the total page table size for a system running 5 applications that utilize half of the memory available, given a two level page table approach with 256 entries. Assume each entry of the main page table is 6 bytes. Calculate the minimum and maximum amount of memory required.

6. A cache designer wants to increase the size of a 4 KiB virtually indexed, physically tagged cache. Given the page size shown above, is it possible to make a 16 KiB direct-mapped cache, assuming 2 words per block? How would the designer increase the data size of the cache?

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Physical Page Valid Tag Number 11 12 4 3 6. 4 9. Virtual Address Size Page Size Page Table Entry Size 32 bits 4 bytes 8 KİB