Question #$1(10$ pts$)$

From P&H p$289,$ Fig $4\mathrm{.}35$ shows the presence of $$register buffers$($shown in blue$)$ between each of the pipeline stages. The caption says the IF$/$ID buffer must be $64$ bits wide to accommodate all data going through that pipeline stage, which here includes both the $32-$bit instruction and the $32-$bit incremented PC$.$

The caption states the width of the other buffer stages are $128$ bits for ID$/$EX$,97$ bits for EX$/$MEM$,$ and $64$ bits for MEM$/$WB$.$