Question 1. (20 points) Consider a cache with 64 blocks and a block size of 8 bytes. Using direct memory mapping, to what block number does byte address 1024 map? Question 2. (15+15-30 points) a. Define the steps to be taken on an instruction cache miss b. Distinguish among, write through and write back. Question 3. (20+10-30 points) Assume the miss rate of an instruction cache is 490 and the miss rate of the data cache is 10%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 100 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 40% Find the average memory access time(AMAT) for a processor with a 1 ns clock cycle time, a miss penalty of 40 clock cycles, instruction miss rate of 10%, and a cache access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls a. b. Question 4. (20 points) Configure an eight-block cache as direct mapped, two-way set associative, four-way set associative, and fully associative