Question$-1$:

a$.$ For a Direct mapped cache, the cache has $4$ blocks with each block containing $1$ word. Fill out the following table below to show the cache's state after the CPU accesses each of the following memory addresses in sequence: $\backslash (0,2,0,4,0\backslash ).$ As an example, the table is filled for the first address. Assume that the cache is empty at the beginning. Also, report the overall hit ratio.

$[30$ points$]$

Answer:

$\backslash$begin$\{$tabular$\}\{|$c$|$c$|$c$|$c$|$c$|$c$|$c$|\}$

$\backslash$hline $\backslash$multirow$[$t$]\{2\}\{*\}\{$Memory Address$\}$ & $\backslash$multirow$[$t$]\{2\}\{*\}\{$Cache Index$\}$ & $\backslash$multirow$[$t$]\{2\}\{*\}\{$Hit or Miss$\}$ & $\backslash$multicolumn$\{4\}\{|$l$|\}\{$Cache content after Access$\}\backslash \backslash$

$\backslash$hline & & & Block $0$ & Block $1$ & Block $2$ & Block $3\backslash \backslash$

$\backslash$hline $0$ & $0$ & Miss & Mem$[0]$ & $-$ & $-$ & $-\backslash \backslash$

$\backslash$hline $2$ & $2$ & Miss & Mem$[0]$ & $-$ & Mem$[2]$ & $-\backslash \backslash$

$\backslash$hline $0$ & $0$ & Hit & Mem$[0]$ & $-$ & Mem$[2]$ & $-\backslash \backslash$

$\backslash$hline $4$ & $0$ & Miss & Mem$[4]$ & $-$ & Mem$[2]$ & $-\backslash \backslash$

$\backslash$hline $0$ & $0$ & Miss & Mem$[0]$ & $-$ & Mem$[2]$ & $-\backslash \backslash$

$\backslash$hline

$\backslash$end$\{$tabular$\}$

No of Hits $=1$

No of Misses $\backslash (=4\backslash )$

Total Accesses $=5$

Hit Ratio $=$ No of Hits $\backslash (/\backslash )$ Total Accesses $=1/5$

Miss Ratio $=$ No of Misses $\backslash (/\backslash )$ Total Accesses $\backslash (=4/5\backslash )$