Question $1$a$.$ Use an FSM to implement a counter with RESET and ENABLE functions. The counter should meet the following requirements: $(1)$ The counter counts downward, $\backslash (0,3,2,1,0,3,2,1\backslash ),$ etc.; $(2)$ The RESET is asynchronous and not synchronized with the CLOCK signal. If RESET signal is low, the counter resets to $0$ ; $(3)$ When ENABLE$=0,$ the counter pauses. Otherwise, it resumes counting.

Please provide the FSM bubble diagram, state table, K$-$Maps, and schematic for the counter.